TD-SCDMA is a 3G standard adopted by the International Telecommunication Union (ITU). It takes advantage of TDMA and synchronous CDMA and provides high spectrum efficiency and service flexibility. In a TD-SCDMA system, it is very important that user equipment (UE) is synchronized to the received signal from Node-B. In general, signal synchronization can be divided into two stages: final synchronization and synchronization tracking. The base of synchronization is on a chip level. Every chip in Node-B is shaped into an ISI-free waveform by using a shaping filter, as shown in FIG. 1. Denote the waveform function of an RRC filter as f(t). In a UE system, to acquire the maximum SINRN, the UE should sample at the peak of the chip waveform, corresponding to time=0 in FIG. 1. In TD-SCDMA, there are two sub-frames in each radio frame, which is of ten milliseconds (10 ms) length. The sub-frame format is shown in FIG. 2. In a sub-frame, there are seven common time slots and two special time slots. The two special time slots include DwPTS and UpPTS. In FIG. 3, the structure of a common time slot is shown. There are two data parts in one time slot, and in the middle of the two data parts, there is a midamble part. The midamble is used to estimate the radio multi-path and is also quite important in maintaining the downlink synchronization.
After having acquired the initial synchronization of the downlink signal, the UE enters into the stage of keeping the synchronization. Because the UE does not know the exact time offset information between the local timer and the downlink signal from Node-B, traditionally an X-times sampling rate is used, where X is an integer larger than 1, i.e. 2, 4 or even 8. Then the UE uses an RRC filter to filter the sample stream. The filter output will shape an auto-correlation waveform of SYNC-DL. The highest peak corresponds to the most likely synchronization point. Using the method, the synchronization time error will be within [−Tc/2X, Tc/2X]. “Early/late gate” is a commonly seen implementation according to the theory set forth above. Another commonly used synchronization method is “τ dithering loop”.
Because a high value of the sample multiple X raises the speed requirement for an analog to digital (A/D) converter, bigger buffer size and computation complexity are required. Bigger buffer size and computation complexity will raise the cost of the hardware system and the consumption of the A/D conversion. So in general, a smaller sample multiple X is better, but if the sample multiple X is too small, then the synchronization precision will decrease. Therefore, the sample multiple X is often set to a value of four (4).